leo47007/TPU-Tensor-Processing-Unit

Berkeley's Spatial Array Generator

GEMM and GEMM-Ops accelerator for PULP systems

Tile based architecture designed for computing efficiency, scalability and generality

An AI accelerator implementation with Xilinx FPGA

The shortest path from PyTorch to custom ASICs.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

🪙 TT-NN operator library, and TT-Metalium low level kernel programming model.

An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge