riscv-software-src/opensbi

RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see firmware folder.

Read-only mirror of https://review.coreboot.org/coreboot.git. Synced every hour. We don't handle Pull Requests.

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

Spike, a RISC-V ISA Simulator

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

The RISC-V Virtual Machine

"Das U-Boot" Source Tree

Open-source high-performance RISC-V processor

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform