Footer

Your go-to destination for discovering trending open-source projects and uncovering the insights that matter

Legal

  • Terms and conditions
  • Privacy policy

More

  • Pricing
  • Advertise
  • onedump
  • gosnakego
  • Contact us

Social

  • X (Twitter)
  • GitHub
Trendshift owl
What they build speaks louder than words
© 2026 Trendshift, created by Julian Li with ❤️
SignalAdvertise
Trendshift
SignalAdvertise
Sign in
Trendshift owl

Discover trends that matter

DailyWeeklyMonthlyYearly
Live mentionsTopics
RepositoriesDevelopers
InsightsStats

ClawBench
ClawBench
Bifrost
Bifrost
Busbar
Busbar

siliconcompiler/scgallery

SiliconCompiler Design Gallery

Visit GitHub
Verilog
80
11
4 contributors
Apache License 2.0
AchievementsView all →
FeaturedAdvertise to 180K+ monthly visitors
ClawBench

a benchmark for personal agents

Bifrost

Enterprise AI Gateway Built For Scale: Route, Govern, and Secure All Your AI Traffic

Busbar

Control what AI can do before it acts

Momentum

How fast siliconcompiler/scgallery is gaining stars, and where it lands on Trendshift and GitHub Trending

Activity and trending

Stars, forks and merged pull requests each day or month, lined up with the repository's rank on Trendshift Trending

Aug 28 – Oct 22, 2026

Stars +4 in 56 days

01
1

Forks +2 in 56 days

01
1

Merged PRs 7 in 56 days

012
2

Trendshift Trendingwhere the repository ranked each day it made the top 25

Top 25 in Verilog

1381419
Aug 28Sep 4Sep 11Sep 18Sep 25Oct 2Oct 9Oct 16
The left and right arrow keys step from day to day; Home and End go to the first and the last

Stars, forks, merged pull requests and Trendshift Trending rank, by day
DayStars gainedForks gainedMerged PRsVerilog
Fri, Aug 28, 2026+0+01Not trending
Sat, Aug 29, 2026+1+00#13
Sun, Aug 30, 2026+0+00Not trending
Mon, Aug 31, 2026+0+00Not trending
Tue, Sep 1, 2026+0+00Not trending
Wed, Sep 2, 2026+0+00Not trending
Thu, Sep 3, 2026+0+00Not trending
Fri, Sep 4, 2026+1+02#8
Sat, Sep 5, 2026+0+00Not trending
Sun, Sep 6, 2026+0+00Not trending
Mon, Sep 7, 2026+0+00Not trending
Tue, Sep 8, 2026+0+00Not trending
Wed, Sep 9, 2026+0+00Not trending
Thu, Sep 10, 2026+0+00Not trending
Fri, Sep 11, 2026+0+00Not trending
Sat, Sep 12, 2026+0+00Not trending
Sun, Sep 13, 2026+0+00Not trending
Mon, Sep 14, 2026+0+00Not trending
Tue, Sep 15, 2026+0+00Not trending
Wed, Sep 16, 2026+0+00Not trending
Thu, Sep 17, 2026+0+00Not trending
Fri, Sep 18, 2026+0+00Not trending
Sat, Sep 19, 2026+0+00Not trending
Sun, Sep 20, 2026+0+00Not trending
Mon, Sep 21, 2026+0+00Not trending
Tue, Sep 22, 2026+0+00Not trending
Wed, Sep 23, 2026+0+00Not trending
Thu, Sep 24, 2026+0+00Not trending
Fri, Sep 25, 2026+0+00Not trending
Sat, Sep 26, 2026+0+00Not trending
Sun, Sep 27, 2026+0+00Not trending
Mon, Sep 28, 2026+0+01Not trending
Tue, Sep 29, 2026+1+10#14
Wed, Sep 30, 2026+0+00Not trending
Thu, Oct 1, 2026+0+01Not trending
Fri, Oct 2, 2026+0+00Not trending
Sat, Oct 3, 2026+0+01Not trending
Sun, Oct 4, 2026+0+00Not trending
Mon, Oct 5, 2026+0+00Not trending
Tue, Oct 6, 2026+0+00Not trending
Wed, Oct 7, 2026+0+00Not trending
Thu, Oct 8, 2026+0+00Not trending
Fri, Oct 9, 2026+0+00Not trending
Sat, Oct 10, 2026+0+00Not trending
Sun, Oct 11, 2026+0+00Not trending
Mon, Oct 12, 2026+0+01Not trending
Tue, Oct 13, 2026+0+00Not trending
Wed, Oct 14, 2026+0+00Not trending
Thu, Oct 15, 2026+0+00Not trending
Fri, Oct 16, 2026+0+00Not trending
Sat, Oct 17, 2026+1+10#19
Sun, Oct 18, 2026+0+00Not trending
Mon, Oct 19, 2026+0+00Not trending
Tue, Oct 20, 2026+0+00Not trending
Wed, Oct 21, 2026+0+00Not trending
Thu, Oct 22, 2026+0+00Not trending
Total+4+27
  • 1#1 on the list
  • 7Rank that day
  • Not trending

Achievements

Trendshift snapshots GitHub's daily Trending list and runs its own trending list

Trendshift Trending

siliconcompiler/scgallery has trended on Trendshift's daily list

Daily

First achieved on 4th, Sep 2026 for Verilog

#8 Verilog Repository Of The Day

First achieved on 4th, Sep 2026 for Verilog

#8 Verilog Repository Of The Day

You might also like

Repositories close to siliconcompiler/scgallery
FeaturedAdvertise to 180K+ monthly visitors
ClawBench

a benchmark for personal agents

Busbar

Control what AI can do before it acts

Bifrost

Enterprise AI Gateway Built For Scale: Route, Govern, and Secure All Your AI Traffic

The-OpenROAD-Project/OpenROAD-flow-scripts

Verilog

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

776528

gdsfactory/gdsfactory

Python

A Python library for designing chips (Photonics, Analog, Quantum, MEMS), PCBs, and 3D-printable objects. We aim to make hardware design accessible, intuitive, and fun—empowering everyone to build the future.

1.1k445

The-OpenROAD-Project/OpenROAD

Verilog

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

3.2k1k

UCSBarchlab/PyRTL

Python

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

30493

intel/rohd-hcl

Dart

A hardware component library developed with ROHD.

11738

sifive/duh

JavaScript

👾 Design ∪ Hardware

795

heitzmann/gdstk

C++

Gdstk (GDSII Tool Kit) is a C++/Python library for creation and manipulation of GDSII and OASIS files.

505109

siliconcompiler/lambdapdk

SourcePawn

A library of open PDK packages

13818

bespoke-silicon-group/basejump_stl

SystemVerilog

BaseJump STL: A Standard Template Library for SystemVerilog

691118