baochip/baochip-1x

OpenTitan: Open source silicon root of trust

BaseJump STL: A Standard Template Library for SystemVerilog

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Rocket Chip Generator

Open-source high-performance RISC-V processor

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

Build your hardware, easily!