Nero7991/llm.vhdl

An inference chip design that runs a real LLM (Qwen2.5-0.5B) on FPGA — one transformer decoder layer in RTL, every silicon value bit-exact against a golden model. 0.56 tok/s measured, a 140× climb, full evidence trail.

reinvented groq LPU, built to run inference on MicroGPT

From-scratch C++/CUDA inference engine for Qwen3-8B

A custom inference engine tuned for Qwen4 architecture. Currently runs Qwen3.8-Flash-Next at 15+ tok/s on 16GB of VRAM and 30 GB of RAM

FINN+ is an extended version of FINN, a dataflow compiler for QNN inference on FPGAs. It is maintained by a group of researchers at Paderborn University, Germany.

Source-available C++/CUDA inference engine for Qwen3.8-27B INT4 on 3x RTX 3090

One line of NInfer for the Blackwell, Ada Lovelace, Ampere, Turing and Volta NVIDIA GPUs, consolidated from the forks that carry it: GGUF block formats, ternary Bonsai 2, device route profiles, MTP and DFlash2.