YosysHQ/sby

Yosys Open SYnthesis Suite

cocotb: Python-based chip (RTL) verification

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

SystemVerilog to Verilog conversion

Multi-platform nightly builds of open source digital design and verification tools

ABC: System for Sequential Logic Synthesis and Formal Verification

Verilator open-source SystemVerilog simulator and lint system

VHDL synthesis (based on ghdl)

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX