veryl-lang/veryl

Chisel: A Modern Hardware Design Language

Haskell to VHDL/Verilog/SystemVerilog compiler

A modern hardware definition language and toolchain based on Python

Scala based HDL

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

Yosys Open SYnthesis Suite

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

cocotb: Python-based chip (RTL) verification