MikePopoloski/slang

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

SystemVerilog language server

Verilator open-source SystemVerilog simulator and lint system

Icarus Verilog

A fast VHDL language server and analysis library written in Rust

Veryl: A Modern Hardware Description Language

All in one vscode plugin for HDL development

SystemVerilog to Verilog conversion