dalance/svls

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

SystemVerilog compiler and language services

A fast VHDL language server and analysis library written in Rust

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

All in one vscode plugin for HDL development

Verilator open-source SystemVerilog simulator and lint system

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

The Svelte Language Server, and official extensions which use it

SystemVerilog to Verilog conversion