verilog-to-routing/vtr-verilog-to-routing

nextpnr portable FPGA place and route tool

Yosys Open SYnthesis Suite

❄️ Visual editor for open FPGA boards

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Multi-platform nightly builds of open source digital design and verification tools

Build your hardware, easily!

VHDL 2008/93/87 simulator

Icarus Verilog

XLS: Accelerated HW Synthesis