YosysHQ/nextpnr

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Universal utility for programming FPGA

Build your hardware, easily!

Package manager and build abstraction tool for FPGA/ASIC development

❄️ Visual editor for open FPGA boards

Yosys Open SYnthesis Suite

Multi-platform nightly builds of open source digital design and verification tools

A modern hardware definition language and toolchain based on Python

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/