VLSIDA/OpenRAM

ASIC implementation flow infrastructure, successor to OpenLane

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

An Open-source FPGA IP Generator

Magic VLSI Layout Tool

Yosys Open SYnthesis Suite

BaseJump STL: A Standard Template Library for SystemVerilog

Small footprint and configurable DRAM core

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more