intel/systemc-compiler

SystemVerilog to Verilog conversion

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Verilator open-source SystemVerilog simulator and lint system

SystemC Reference Implementation

Yosys Open SYnthesis Suite

SystemVerilog design elaborator into word-level netlist form

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

BaseJump STL: A Standard Template Library for SystemVerilog