chipsalliance/UHDM

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Verilator open-source SystemVerilog simulator and lint system

SystemC Reference Implementation

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

BaseJump STL: A Standard Template Library for SystemVerilog

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

The UVM written in Python

Circuit IR Compilers and Tools

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework