chipsalliance/uvm-verilator

The UVM written in Python

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Functional verification project for the CORE-V family of RISC-V cores.

SystemC Reference Implementation

cocotb: Python-based chip (RTL) verification

Verilator open-source SystemVerilog simulator and lint system

The MyHDL development repository

Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.