SpinalHDL/VexiiRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

RSD: RISC-V Out-of-Order Superscalar Processor

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

3-stage RV32IMACZb* processor with debug

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

PicoRV32 - A Size-Optimized RISC-V CPU

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.