pulp-platform/cheshire

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

A Linux-capable RISC-V multicore for and by the world

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V

RISC-V SoC designed by students in UCAS

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

NucleusRV (RV32-IMAFC) - A 32-bit 5 staged pipelined risc-v core.