ghdl/ghdl-yosys-plugin

VHDL 2008/93/87 simulator

Yosys Open SYnthesis Suite

SystemVerilog to Verilog conversion

Multi-platform nightly builds of open source digital design and verification tools

All in one vscode plugin for HDL development

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

nextpnr portable FPGA place and route tool

Haskell to VHDL/Verilog/SystemVerilog compiler

Verilog to Routing -- Open Source CAD Flow for FPGA Research