ghdl/ghdl

Verilator open-source SystemVerilog simulator and lint system

cocotb: Python-based chip (RTL) verification

Yosys Open SYnthesis Suite

Icarus Verilog

Haskell to VHDL/Verilog/SystemVerilog compiler

Multi-platform nightly builds of open source digital design and verification tools

Verilog to Routing -- Open Source CAD Flow for FPGA Research

XLS: Accelerated HW Synthesis

Package manager and build abstraction tool for FPGA/ASIC development