OSVVM/OSVVM

VUnit is a unit testing framework for VHDL/SystemVerilog

cocotb: Python-based chip (RTL) verification

The UVM written in Python

Style guide enforcement for VHDL

Test suite designed to check compliance with the SystemVerilog standard.

VHDL 2008/93/87 simulator

Verilator open-source SystemVerilog simulator and lint system

BaseJump STL: A Standard Template Library for SystemVerilog

A fast VHDL language server and analysis library written in Rust