VUnit/vunit

cocotb: Python-based chip (RTL) verification

Verilator open-source SystemVerilog simulator and lint system

VHDL 2008/93/87 simulator

The UVM written in Python

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

The MyHDL development repository