Digital-EDA/Digital-IDE

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A fast VHDL language server and analysis library written in Rust

VHDL 2008/93/87 simulator

Verilator open-source SystemVerilog simulator and lint system

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

cocotb: Python-based chip (RTL) verification

SystemVerilog language server

Veryl: A Modern Hardware Description Language

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX