suoto/hdl_checker

Style guide enforcement for VHDL

All in one vscode plugin for HDL development

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A fast VHDL language server and analysis library written in Rust

Verilog/SystemVerilog support for VS Code

A curated list of awesome resources for HDL design and verification

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

A SystemVerilog language server based on the Slang library.

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server