SystemRDL/systemrdl-compiler

Control and status register code generator toolchain

Code generation tool for control and status registers

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Generate address space documentation HTML from compiled SystemRDL input

An open-source HDL register code generator fast enough to run in real time.

ARCH hardware description language and compiler

An open-source implementation of the VADL processor description language.

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Generate Rust register maps (`struct`s) from SVD files