Laboratory course on RISC-V Processor Development
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
A RISC-V Core (RV32I) written in Chisel HDL
Learning FPGA, yosys, nextpnr, and RISC-V
NucleusRV (RV32-IMAFC) - A 32-bit 5 staged pipelined risc-v core.
Материалы для курсов по проектированию цифровых вычислительных систем
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
