OpenXiangShan/XiangShan

PicoRV32 - A Size-Optimized RISC-V CPU

A FPGA friendly 32 bit RISC-V CPU implementation

Rocket Chip Generator

A graphical processor simulator and assembly editor for the RISC-V ISA

RISC-V Instruction Set Manual

GNU toolchain for RISC-V, including GCC

Learning FPGA, yosys, nextpnr, and RISC-V

OpenTitan: Open source silicon root of trust

Build your hardware, easily!