wyvernSemi/riscV

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A RISC-V Core (RV32I) written in Chisel HDL

Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32IM ISA.

Open-source high-performance RISC-V processor

Laboratorio de Arquitectura de Ordenadores.Procesador RISC-V de 32 bits

NucleusRV (RV32-IMAFC) - A 32-bit 5 staged pipelined risc-v core.

3-stage RV32IMACZb* processor with debug

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RSD: RISC-V Out-of-Order Superscalar Processor