oscar30gt/pulse

VHDL 2008/93/87 simulator

VHDL compiler and simulator

Free, open-source EDA platform for VHDL and Verilog. HDL editor, circuit canvas, RTL viewer, waveform viewer, and FPGA toolchain in one window.

Digital logic design tool and simulator

Verilator open-source SystemVerilog simulator and lint system

All in one vscode plugin for HDL development

cocotb: Python-based chip (RTL) verification

Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively

A digital logic designer and circuit simulator.