XS-MLVP/UCAgent

Digital HDL Design Full-stack Agents

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

Bridge between LLM-Agent and Cadence Virtuoso. A new infrastructure for Agentic Analog and Mixed-Signal Design.

Test suite designed to check compliance with the SystemVerilog standard.

An open-source collection of embedded development and debugging skills for Claude Code, Copilot, TRAE, and other AI coding assistants that support the Skill protocol. Once installed, the AI assistant can directly operate compilers, debuggers, and communication buses, automating the full workflow from code generation to hardware verification.

The UVM written in Python

Style guide enforcement for VHDL

Repurposing existing HDL tools to help writing better code

Hardware testing for the software world. Real or virtual, local or remote, human, automated or agentic.