iammituraj/pequeno_riscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

PicoRV32 - A Size-Optimized RISC-V CPU

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

3-stage RV32IMACZb* processor with debug

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.