ucb-bar/testchipip

For contributions of Chisel IP to the chisel community.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Rocket Chip Generator

Baochip 1x Silicon

CORE-ET Silicon Platform

BaseJump STL: A Standard Template Library for SystemVerilog

An open-source UCIe implementation

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A hardware component library developed with ROHD.