ucb-bar/ucie

For contributions of Chisel IP to the chisel community.

ASIC implementation flow infrastructure, successor to OpenLane

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Rocket Chip Generator

Baochip 1x Silicon

ElemRV - End-to-end Open-Source RISC-V Microcontroller

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI...

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform