Logic-Design-Services/CTU-CAN-FD

A huge VHDL library for FPGA and digital ASIC development

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Small footprint and configurable Ethernet core

BaseJump STL: A Standard Template Library for SystemVerilog

A new high quality, speed optmimized firmware for CANable adapters with lots of new features.

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!