BerkeleyLab/Bedrock

A huge VHDL library for FPGA and digital ASIC development

HDL libraries and projects

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Verilog HDL files

A curated list of awesome resources for HDL design and verification

BaseJump STL: A Standard Template Library for SystemVerilog

A hardware component library developed with ROHD.

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A Python package to use FPGA development tools programmatically.