fpganinja/taxi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

BaseJump STL: A Standard Template Library for SystemVerilog

Bus bridges and other odds and ends

A huge VHDL library for FPGA and digital ASIC development

Build your hardware, easily!

Open Logic FPGA Standard Library

Common SystemVerilog components

Small footprint and configurable PCIe core

🌱 Open source ecosystem for open FPGA boards