open-logic/open-logic

A huge VHDL library for FPGA and digital ASIC development

HDL libraries and projects

BaseJump STL: A Standard Template Library for SystemVerilog

Common SystemVerilog components

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

VHDL 2008/93/87 simulator

🌱 Open source ecosystem for open FPGA boards

Package manager and build abstraction tool for FPGA/ASIC development

Hardcaml is an OCaml library for designing hardware.