pulp-platform/common_cells

BaseJump STL: A Standard Template Library for SystemVerilog

Open Logic FPGA Standard Library

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

SystemC Reference Implementation

A huge VHDL library for FPGA and digital ASIC development

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

HDL libraries and projects

The MyHDL development repository