enjoy-digital/litesata

Small footprint and configurable PCIe core

Small footprint and configurable SDCard core

Small footprint and configurable DRAM core

Small footprint and configurable Ethernet core

A huge VHDL library for FPGA and digital ASIC development

Build your hardware, easily!

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Small footprint and configurable embedded FPGA logic analyzer

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI...