chili-chips-ba/openCologne-PCIE

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to Gbps SerDes. Now for the first time in opensource on the Host side too. Our project roots for the Root Port in 4 ways: |1| openRTL |2| openBFM with unique SIM and WAVE capabilities, way better than vendor's |3| openSW stack |4| one-of-a-kind open backplane.

Small footprint and configurable PCIe core

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Open source FPGA silicon

Example designs for FPGA Drive FMC

PCILeech firmware generator tool

Automatically generates custom pcileech firmware locally from real pcie devices

ElemRV - End-to-end Open-Source RISC-V Microcontroller

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!