Footer

Your go-to destination for discovering trending open-source projects and uncovering the insights that matter

Legal

  • Terms and conditions
  • Privacy policy

More

  • Pricing
  • Advertise
  • onedump
  • gosnakego
  • Contact us

Social

  • X (Twitter)
  • GitHub
Trendshift owl
What they build speaks louder than words
© 2026 Trendshift, created by Julian Li with ❤️
SignalAdvertise
Trendshift
SignalAdvertise
Sign in
Trendshift owl

Discover trends that matter

DailyWeeklyMonthlyYearly
Live mentionsTopics
RepositoriesDevelopers
InsightsStats
Bifrost
Bifrost
Busbar
Busbar
AxiomCode
AxiomCode

open-sdr/openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Visit GitHub
Verilog
912
301
11 contributors
GNU Affero General Public License v3.0
AchievementsView all →
FeaturedAdvertise to 180K+ monthly visitors
Bifrost

Enterprise AI Gateway Built For Scale: Route, Govern, and Secure All Your AI Traffic

Busbar

Control what AI can do before it acts

AxiomCode

Give Al Agents a Deeper Understanding of Your Codebase with a Code Graph

Momentum

How fast open-sdr/openwifi-hw is gaining stars, and where it lands on Trendshift and GitHub Trending

Activity and trending

Stars, forks and merged pull requests each day or month, lined up with the repository's rank on Trendshift Trending

Oct 12 – Oct 20, 2026

Stars +1 in 9 days

01
1

Forks +0 in 9 days

01

Merged PRs 1 in 9 days

01
1

Trendshift Trendingwhere the repository ranked each day it made the top 25

Top 25 in Verilog

23
Oct 12Oct 14Oct 16Oct 18Oct 20
The left and right arrow keys step from day to day; Home and End go to the first and the last

Stars, forks, merged pull requests and Trendshift Trending rank, by day
DayStars gainedForks gainedMerged PRsVerilog
Mon, Oct 12, 2026+0+00Not trending
Tue, Oct 13, 2026+0+01Not trending
Wed, Oct 14, 2026+0+00Not trending
Thu, Oct 15, 2026+1+00#23
Fri, Oct 16, 2026+0+00Not trending
Sat, Oct 17, 2026+0+00Not trending
Sun, Oct 18, 2026+0+00Not trending
Mon, Oct 19, 2026+0+00Not trending
Tue, Oct 20, 2026+0+00Not trending
Total+1+01
  • 1#1 on the list
  • 7Rank that day
  • Not trending

Achievements

Trendshift snapshots GitHub's daily Trending list and runs its own trending list

Trendshift Trending

open-sdr/openwifi-hw has trended on Trendshift's daily list

Daily

First achieved on 15th, Oct 2026 for Verilog

#23 Verilog Repository Of The Day

First achieved on 15th, Oct 2026 for Verilog

#23 Verilog Repository Of The Day

You might also like

Repositories close to open-sdr/openwifi-hw
FeaturedAdvertise to 180K+ monthly visitors
AxiomCode

Give Al Agents a Deeper Understanding of Your Codebase with a Code Graph

Bifrost

Enterprise AI Gateway Built For Scale: Route, Govern, and Secure All Your AI Traffic

Busbar

Control what AI can do before it acts

open-sdr/openwifi

C

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

4.8k808

greatscottgadgets/hackrf

C

low cost software radio platform

8.2k1.7k

FujiNetWIFI/fujinet-hardware

Python

Schematics and design files for FujiNet hardware

13927

EttusResearch/uhd

Verilog

The USRP™ Hardware Driver Repository

1.3k763

enjoy-digital/litex_m2sdr

C

LiteX based M2 SDR/RF FPGA board.

22942

Telecominfraproject/wlan-ap

C
209132

ConstStrings/GoWinSDR

Verilog

基于高云FPGA与AD9363/AD9361射频收发器,构建了一套灵活可重构的软件无线电(SDR)系统,通信核心代码纯Verilog实现。软硬件全开源,高速基带处理部署于FPGA,交互业务部署于Python上位机,通过千兆以太网交互,实现了QPSK等多种实时通信与动态参数配置 Based on the Gowin FPGA and AD9363/AD9361 RF transceiver, a flexible and reconfigurable Software Defined Radio (SDR) system has been built, with the communication core implemented entirely in Verilog.

16029

FPGAwars/apio

Python

🌱 Open source ecosystem for open FPGA boards

1k160

fpganinja/taxi

SystemVerilog

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

981151