pulp-platform/FlooNoC

Tile based architecture designed for computing efficiency, scalability and generality

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Get Started From Here. The main repo for the whole open-rdma project. Including introduction, hands-on guide, new events and many other things.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

An Open-source FPGA IP Generator

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

Berkeley's Spatial Array Generator

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

ASIC implementation flow infrastructure, successor to OpenLane