bespoke-silicon-group/bsg_manycore

A Fast, Low-Overhead On-chip Network

A Linux-capable RISC-V multicore for and by the world

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Berkeley's Spatial Array Generator

The official repository for the gem5 computer-system architecture simulator.

A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

Baochip 1x Silicon

eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V