pulp-platform/axi

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Bus bridges and other odds and ends

AMBA AXI VIP

BaseJump STL: A Standard Template Library for SystemVerilog

A huge VHDL library for FPGA and digital ASIC development

Build your hardware, easily!

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility