Footer

Your go-to destination for discovering trending open-source projects and uncovering the insights that matter

Legal

  • Terms and conditions
  • Privacy policy

More

  • Pricing
  • Advertise
  • onedump
  • gosnakego
  • Contact us

Social

  • X (Twitter)
  • GitHub
Trendshift owl
What they build speaks louder than words
© 2026 Trendshift, created by Julian Li with ❤️
SignalAdvertise
Trendshift
SignalAdvertise
Sign in
Trendshift owl

Discover trends that matter

DailyWeeklyMonthlyYearly
Live mentionsTopics
RepositoriesDevelopers
InsightsStats
ClawBench
ClawBench
Bifrost
Bifrost
Busbar
Busbar

TinyTapeout/ttihp-verilog-template

Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects

Visit GitHub
Verilog
84
211
6 contributors
Apache License 2.0
website
AchievementsView all →
FeaturedAdvertise to 180K+ monthly visitors
ClawBench

a benchmark for personal agents

Bifrost

Enterprise AI Gateway Built For Scale: Route, Govern, and Secure All Your AI Traffic

Busbar

Control what AI can do before it acts

Momentum

How fast TinyTapeout/ttihp-verilog-template is gaining stars, and where it lands on Trendshift and GitHub Trending

Activity and trending

Stars, forks and merged pull requests each day or month, lined up with the repository's rank on Trendshift Trending

Aug 23 – Oct 22, 2026

Stars +41 in 61 days

0510
9

Forks +55 in 61 days

0246
6

Merged PRs 0 in 61 days

01

Trendshift Trendingwhere the repository ranked each day it made the top 25

Top 25 in Verilog

591615227211823220141117813121181919251122102524967133
Aug 23Aug 31Sep 8Sep 16Sep 24Oct 2Oct 10Oct 18
The left and right arrow keys step from day to day; Home and End go to the first and the last

Stars, forks, merged pull requests and Trendshift Trending rank, by day
DayStars gainedForks gainedMerged PRsVerilog
Sun, Aug 23, 2026+1+00#5
Mon, Aug 24, 2026+1+10#9
Tue, Aug 25, 2026+0+00Not trending
Wed, Aug 26, 2026+0+00Not trending
Thu, Aug 27, 2026+1+00#16
Fri, Aug 28, 2026+0+00Not trending
Sat, Aug 29, 2026+1+00#15
Sun, Aug 30, 2026+0+00Not trending
Mon, Aug 31, 2026+0+00Not trending
Tue, Sep 1, 2026+0+00Not trending
Wed, Sep 2, 2026+0+00Not trending
Thu, Sep 3, 2026+0+20#22
Fri, Sep 4, 2026+0+00Not trending
Sat, Sep 5, 2026+1+10#7
Sun, Sep 6, 2026+0+00Not trending
Mon, Sep 7, 2026+0+00Not trending
Tue, Sep 8, 2026+0+10#21
Wed, Sep 9, 2026+0+20#18
Thu, Sep 10, 2026+0+20#23
Fri, Sep 11, 2026+1+60#2
Sat, Sep 12, 2026+0+00Not trending
Sun, Sep 13, 2026+0+10#20
Mon, Sep 14, 2026+9+00#1
Tue, Sep 15, 2026+3+20#4
Wed, Sep 16, 2026+2+40#11
Thu, Sep 17, 2026+1+20#17
Fri, Sep 18, 2026+2+20#8
Sat, Sep 19, 2026+1+30#13
Sun, Sep 20, 2026+5+20#1
Mon, Sep 21, 2026+1+30#21
Tue, Sep 22, 2026+1+20#18
Wed, Sep 23, 2026+0+10#19
Thu, Sep 24, 2026+0+00Not trending
Fri, Sep 25, 2026+0+00Not trending
Sat, Sep 26, 2026+0+10#19
Sun, Sep 27, 2026+0+10Not trending
Mon, Sep 28, 2026+0+00Not trending
Tue, Sep 29, 2026+0+30#25
Wed, Sep 30, 2026+0+00Not trending
Thu, Oct 1, 2026+1+10#11
Fri, Oct 2, 2026+0+20Not trending
Sat, Oct 3, 2026+0+10#22
Sun, Oct 4, 2026+0+00Not trending
Mon, Oct 5, 2026+1+00#10
Tue, Oct 6, 2026+0+20#25
Wed, Oct 7, 2026+0+10#24
Thu, Oct 8, 2026+1+00#9
Fri, Oct 9, 2026+0+00Not trending
Sat, Oct 10, 2026+1+10#6
Sun, Oct 11, 2026+0+10Not trending
Mon, Oct 12, 2026+1+10#7
Tue, Oct 13, 2026+1+10#13
Wed, Oct 14, 2026+0+00Not trending
Thu, Oct 15, 2026+0+00Not trending
Fri, Oct 16, 2026+3+10#3
Sat, Oct 17, 2026+0+10Not trending
Sun, Oct 18, 2026+0+00Not trending
Mon, Oct 19, 2026+0+00Not trending
Tue, Oct 20, 2026+0+00Not trending
Wed, Oct 21, 2026+1+00Not trending
Thu, Oct 22, 2026+0+00Not trending
Total+41+550
  • 1#1 on the list
  • 7Rank that day
  • Not trending

    • Mentions and achievements

    Where people are talking about TinyTapeout/ttihp-verilog-template, and every badge it has earned
    1. Jun 281 post

      • I’ve been developing chdl, a C11 shaped language with vast pipeline abilities and common bus interface. Emits to a C-sim and SV. Has full dut test backend too. @splinedrive How do I go from SV to…

        Read full on X, posted by @agentdavo

        @agentdavo · x.com

    You might also like

    Repositories close to TinyTapeout/ttihp-verilog-template
    FeaturedAdvertise to 180K+ monthly visitors
    ClawBench

    a benchmark for personal agents

    Busbar

    Control what AI can do before it acts

    Bifrost

    Enterprise AI Gateway Built For Scale: Route, Govern, and Secure All Your AI Traffic

    TinyTapeout/vga-playground

    JavaScript

    Playground for VGA projects on Tiny Tapeout

    8123

    FPGADude/Digital-Design

    Verilog

    Verilog HDL files

    19262

    hdl/awesome

    Shell

    A curated list of awesome resources for HDL design and verification

    17924

    siliconcompiler/scgallery

    Verilog

    SiliconCompiler Design Gallery

    8011

    bespoke-silicon-group/basejump_stl

    SystemVerilog

    BaseJump STL: A Standard Template Library for SystemVerilog

    691118

    codejunkie99/Gateflow-Plugin

    Python

    AI-powered SystemVerilog development assistant — design, verify, debug, and deliver working RTL with natural language.

    11816

    Weiyet/MakerCode_RTLChallenge

    SystemVerilog

    Public RTL Question Bank of MakerCode https://makercode.jixiao-ai.com/

    10927

    mole99/gf180mcu-fabulous-fpga

    Verilog
    1306

    intel/rohd-hcl

    Dart

    A hardware component library developed with ROHD.

    11738