zeroasiccorp/logikbench

EPFL logic synthesis benchmarks

Digital Design Equivalence Checking

AI-powered SystemVerilog development assistant — design, verify, debug, and deliver working RTL with natural language.

Sequential Logic

ABC: System for Sequential Logic Synthesis and Formal Verification

The HW-CBMC and EBMC Model Checkers for Verilog

Multi-platform nightly builds of open source digital design and verification tools

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

Public RTL Question Bank of MakerCode https://makercode.jixiao-ai.com/