lsils/benchmarks

ABC: System for Sequential Logic Synthesis and Formal Verification

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

An open-source benchmark for generating design RTL with natural language

Digital HDL Design Full-stack Agents

C++ logic network library

A curated list of awesome resources for HDL design and verification

BaseJump STL: A Standard Template Library for SystemVerilog

Multi-platform nightly builds of open source digital design and verification tools

Yosys Open SYnthesis Suite