huawei-csl/rtlscout

RTL agent team; Harness for Agentic hardware design and verificiation.

AI-powered SystemVerilog development assistant — design, verify, debug, and deliver working RTL with natural language.

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

Digital HDL Design Full-stack Agents

ARCH hardware description language and compiler

Codex-first, vendor-neutral RTL coding and verification skill using open-source tools

An open-source benchmark for generating design RTL with natural language

Public RTL Question Bank of MakerCode https://makercode.jixiao-ai.com/

Yosys Open SYnthesis Suite