THU-DSP-LAB/ventus-gpgpu

Open-source high-performance RISC-V processor

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Rocket Chip Generator

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

Like VexRiscv, but, Harder, Better, Faster, Stronger