pulp-platform/spatz

Open-source high-performance RISC-V processor

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

Like VexRiscv, but, Harder, Better, Faster, Stronger

A Linux-capable RISC-V multicore for and by the world

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core