dpretet/async_fifo

Common SystemVerilog components

BaseJump STL: A Standard Template Library for SystemVerilog

A huge VHDL library for FPGA and digital ASIC development

HDL libraries and projects

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Open Logic FPGA Standard Library

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cocotb: Python-based chip (RTL) verification